The present disclosure relates generally to the field of semiconductor manufacturing, and more particularly, to the field of integrated circuit metrology for controlling critical dimensions of features formed on semiconductor wafers.
With the advancement of semiconductor manufacturing, current semiconductor fabrication design rules allow ultra large scale integration (ULSI) devices to possess submicron features, increased transistor and circuit speeds, and improved reliability. To ensure that the devices are of a desired size, e.g., they do not improperly overlap or interact with one another, the design rules define such things as the tolerances between devices and interconnecting lines, and the widths of the lines. The design rule limitation will often define a desired range for line and spacing dimensions, such as the width of a line or the amount of space between two lines permitted in the fabrication of devices.
Frequently, dimensional errors indicate certain instability in a critical part of the semiconductor manufacturing processes. Dimensional errors may arise from any number of sources, such as optical (e.g., lens field curvature or lens aberration in a photolithography system), mechanical, or chemical (e.g., thickness non-uniformity of resist coating and anti-reflection coating (ARC)) sources. In one example, lithography machines, which facilitate pattern projection on wafers, may cause dimensional errors by supplying an incorrect energy amount (e.g., the radiation used for exposure). Accordingly, among other things, it is desirable to provide adequate control of the energy dose to ensure that the dimension complies with the predefined specification.
For those reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved dimension controller.